1. Field of the Invention
The present invention relates to a semiconductor device for generating an internal operational factor corresponding to an external operational factor such as a power supply voltage or a clock signal. More specifically, the present invention relates to a semiconductor device including a phase locked loop (PLL) circuit or a delay locked loop (DLL) circuit or a ring oscillator for generating an internal clock signal and/or a semiconductor device including a down converter for generating an internal power supply potential by down-converting level of an externally applied power supply potential.
2. Description of the Background Art
A PLL circuit has been known as a circuit for generating an internal signal which is in phase/frequency synchronization with an externally applied signal. The PLL circuit is used for reproducing color subcarrier for synchronous detection of a color burst signal in an integrated circuit for reproducing an ATC (Automatic Control) type color subcarrier, for improving stability of color reproduction in a color television. It is also used in the field of wire communication for synchronizing a clock output from a highly stable oscillator arranged in one station with a reference clock received from a high level station so as to distribute stable clock to various communication devices in the station.
FIG. 1 shows a schematic structure of a conventional PLL. Referring to FIG. 1, the PLL circuit includes a phase comparator circuit 2 receiving an internal clock intCLK and an external clock extCLK for outputting control signals UP and /DOWN corresponding to frequency and phase deviation between the internal clock intCLK and the external clock extCLK; a charge pump circuit 3 for adjusting potential level of its output node 3a in accordance with the control signals UP and /DOWN from phase comparator circuit 2; a loop filter 4 for filtering the output signal (potential) from output node 3a of charge pump circuit 3; a current adjusting potential output circuit 5 receiving the output potential VP from loop filter 4 for outputting an output potential VN corresponding to the output potential VP; and a ring oscillator having its oscillation frequency controlled in accordance with the output potential VP from loop filter 4 and the potential VN from current adjusting potential output circuit 5. The internal clock intCLK is output from ring oscillator 6.
Phase comparator 2 has a structure of a phase frequency comparator (PFC) and it sets the control signal UP at an L (low) level when the frequency of the internal clock intCLK is larger than the frequency of the external clock extCLK or when the phase of the internal clock intCLK is in advance of the phase of the external clock extCLK, and it sets the control signal UP at an H (high) level when the frequency of the internal clock intCLK is smaller than the frequency of the external clock extCLK or when the phase of the internal clock intCLK is lagged from that of the external clock extCLK. The control signal /DOWN from the phase comparator circuit 2 is set to the L level when the frequency of the internal clock intCLK is larger than the frequency of external clock extCLK or the phase of internal clock intCLK is in advance of the phase of the external clock extCLK, and it is set to the H level when the frequency of the internal clock intCLK is smaller than the frequency of the external clock extCLK or when the phase of the internal clock intCLK is lagged from the phase of the external clock extCLK. The phase comparator circuit 2 operates as a frequency error detector automatically when unlocked, and operates as a phase difference detector in a capture range.
Charge pump circuit 3 includes a constant current circuit 3c connected between a power supply node 1a to which the power supply potential VCC is applied and a node 3b, for supplying a constant current to node 3b; a p channel MOS (insulated gate type field effect) transistor 3d connected between node 3b and an output node 2a and receiving at its gate the control signal UP from phase comparator circuit; an n channel MOS transistor 3f connected between output node 3a and a node 3e and receiving at its gate the control signal /DOWN from phase comparator circuit 2; and a constant current circuit 3g connected between node 3e and a ground node 1b receiving the ground potential GND for sinking a prescribed constant current. When control signal UP is at the L level and the control signal /DOWN is at the L level, charge pump circuit 3 supplies charges to node 3g, and when control signal UP is at the H level and the control signal /DOWN is at the H level, it sinks charges from node 3a. Loop filter 4 serves as a lowpass filter for removing a high frequency component of potential change at the output node 3a of charge pump circuit 3. Loop filter 4 includes a resistance element 4b connected between output node 3a and node 4a; a resistance element 4d connected between nodes 4a and 4c; and a capacitor 4e connected between node 4c and the ground node 1b. Resistance elements 4b and 4d and the capacitor 4e constitute an RC lowpass filter, and a potential VP corresponding to the potential on output node 3a of charge pump circuit 3 is output from node 4a. 
Current adjusting potential output circuit 5 includes a p channel MOS transistor 5b connected between power supply node 1a and node 5a and having its gate connected to node 4a of loop filter 4; and an n channel MOS transistor 5c connected between node 5a and ground node 1b and having its gate connected to node 5a. The n channel MOS transistor 5c has its gate and drain connected to each other and operates in a saturation region, and therefore it sets the potential at gate 5a in accordance with a current applied from p channel MOS transistor 5b, in accordance with square-law characteristic of (Ids=xcex2(Vgsxe2x88x92Vth)2).
Ring oscillator 6 includes an odd-number of inverters 6a connected in a ring shape, each having driving current (operational current) adjusted in accordance with output potentials VP and VN. These odd-number of inverters 6a have the same structure and denoted by the same reference character. Inverter 6a includes a current adjusting p channel MOS transistor 6ab connected between power supply node 1a and a node 6aa and receiving at its gate the output potential VP from loop filter 4; a p channel MOS transistor 6ae connected between node 6aa and an output node 6ac and having its gate connected to input node 6ad; an n channel MOS transistor 6ad connected between output node 6ac and a node 6af and having its gate connected to input node 6ad; and a current adjusting n channel MOS transistor 6ah connected between node 6af and ground node 1b and receiving at its gate the output potential VN from current adjusting potential output circuit 5. The operation will be briefly described.
When the frequency of the internal clock intCLK is larger than the frequency of external clock extCLK or when the phase of the internal clock intCLK is in advance of the phase of the external clock extCLK, phase comparator circuit 2 sets control signals UP and /DOWN both to the L level. In this state, p channel MOS transistor 3d in charge pump circuit 3 is rendered conductive and n channel MOS transistor 3f is rendered non-conductive. Charges are supplied to output node 3a through p channel MOS transistor 3d which is conductive, the potential at output node 3a rises, and in response, output potential VP at node 4a of loop filter 4 increases. As the output potential VP increases, conductance of p channel MOS transistor 5b in current adjusting potential output circuit 5 becomes smaller, and current flowing therethrough becomes smaller. As the amount of current from MOS transistor 5b becomes smaller, output potential VN at node 5a lowers in response. The output potential VN changes in accordance with the square-law characteristic, and the output voltage VN settles at a level at which the currents flowing through p channel MOS transistor 5b and through n channel MOS transistor 5c become equal to each other.
When output potential VP rises and output potential VN lowers, current flowing through current adjusting p channel MOS transistor 6ab and current adjusting n channel MOS transistor 6ah of inverter 6a in ring oscillator 6 becomes smaller accordingly. Therefore, driving current (charging/discharging current) of inverter 6a becomes smaller, speed of operation of inverter 6a becomes slower, and in response, delay time in inverter 6a increases. As a result, the frequency of the internal clock intCLK output from ring oscillator 6 becomes smaller, the internal clock is generated with a delay in the next cycle, and thus the advance in phase of internal clock intCLK is adjusted.
When the frequency of internal clock intCLK is smaller than the frequency of external clock extCLK or when the phase of internal clock intCLK is lagged from the phase of external clock extCLK, the phase comparator circuit 2 sets the control signals UP and /DOWN both to the H level. The p channel MOS transistor 3d in charge pump circuit 3 is rendered non-conductive by the control signal UP which is at the H level, the n channel MOS transistor 3f is rendered conductive by the control signal /DOWN which is at the H level, charges are extracted from node 3a to the ground node 1b, and the potential at output node 3a lowers. In response, the output potential VP at output node 4a of loop filter 4 lowers. As the output potential VP lowers, conductance of p channel MOS transistor 5b increases in current adjusting potential output circuit 5, current flowing therethrough increases and output potential VN at node 5a increases. The output potential VN is settled at a level where the current flowing through n channel MOS transistor 5c becomes equal to the current flowing through p channel MOS transistor 5e. 
In response to the lowering of output potential VP and the rise of output potential VN, the current flowing through current adjusting p channel MOS transistor 6ab and current adjusting n channel MOS transistor 6ah in each inverter 6a of ring oscillator 6 increases, so that the driving force of inverter 6a increases and in response, delay time of inverter 6a becomes smaller. As a result, the frequency of the internal clock intCLK output from ring oscillator 6 is made larger, and as the frequency increases, a clock is generated at an earlier timing in the next cycle, and thus the delay in phase of the internal clock intCLK can be recovered.
By the above described series of operations, the external clock extCLK and the internal clock intCLK have their phases and/or frequencies made equal by the PLL circuit. The state in which internal clock intCLK has the same frequency and phase as those of external clock extCLK will be referred to as a state in which internal clock intCLK is locked in to the external clock extCLK.
In the conventional PLL circuit shown in FIG. 1, the output potential VP of loop filter 4 is directly applied to p channel MOS transistor 5b of current adjusting potential generating circuit and to the gate of p channel MOS transistor 6ab of inverter 6a of ring oscillator 6. Therefore, only with a small fluctuation of output potential VP, the current flowing through p channel MOS transistors 5b and 5a changes significantly in accordance with the square-law characteristic. Accordingly, current flowing through n channel MOS transistor 5c largely varies, and current flowing through MOS transistor 6ah (MOS transistor for adjusting current of inverter 6a), constituting a current mirror circuit together with the MOS transistor 5c, changes significantly. By the change in current, the delay time of inverter 6a much changes. As a result, only by a small fluctuation of output potential VP from loop filter 4, internal clock intCLK output from ring oscillator 6 changes significantly. Even after the internal clock intCLK is locked in to the external clock extCLK, frequency/phase of internal clock intCLK much fluctuates because of small potential fluctuation at output node 3a of charge pump circuit 3. Accordingly, there arises a problem that the frequency of internal clock intCLK much fluctuates around the external clock extCLK, namely, the jitter of internal clock intCLK becomes larger.
When supply of the external clock extCLK is interrupted, the PLL circuit changes the output potential VP of loop filter 4 so as to lock the internal clock intCLK in the interrupted external clock extCLK, and hence the output potential VP changes significantly. Accordingly, when the external clock extCLK is applied again, it takes long time to lock the internal clock intCLK again in the external clock extCLK.
Further, since internal clock intCLK is generated by using a ring oscillator 6 having an odd-number of stages of inverters 6a connected in a ring, if the frequency of external clock extCLK is high, it becomes difficult for the speed of operation of inverter 6a to follow such high speed external clock extCLK, and thus it becomes difficult to lock the internal clock intCLK in the external clock extCLK.
Further, if the power supply potential VCC fluctuates much, the fluctuation in gate-source voltage (gate-to-source voltage) of p channel MOS transistors 5b and 6ab for current adjustment becomes larger, current flowing through MOS transistors 6ab and 6ah for current adjustment changes accordingly, and frequency of internal clock intCLK changes continuously. Therefore, it becomes difficult to lock the internal clock intCLK in the external clock extCLK, and hence it becomes difficult to generate the internal clock intCLK which has its phase synchronized with the external clock extCLK.
An object of the present invention is to provide a semiconductor device having a clock generator capable of generating an internal clock signal, as a second signal, which is synchronized in phase with (locked in) a stably incoming external signal as a first signal.
Another object of the present invention is to provide a semiconductor device having a clock generator capable of generating an internal clock signal with smaller jitter during locking.
A still another object of the present invention is to provide a semiconductor device having a clock generator capable of outputting an internal clock signal which can be easily locked in a high speed external clock signal.
Further object of the present invention is to provide a semiconductor device having a clock generator capable of generating an internal clock signal which is locked in the external clock signal at high speed when the supply of the external clock signal is interrupted and resumed.
A still further object of the present invention is to provide a power supply potential supplying circuit capable of supplying an internal power supply potential of which fluctuation is suppressed.
According to a first aspect, the present invention includes a difference adjusting circuit for detecting difference in frequency and phase of the external clock signal as the first signal and the internal clock signal as the second signal and for outputting a signal for reducing the difference in accordance with the result of detection; a differential amplifying circuit for differentially amplifying the output signal from the difference adjusting circuit and a feedback potential; and an internal clock signal generating circuit of which operational current is adjusted in accordance with the output signal from the differential amplifying circuit. The feedback potential is generated at a connection portion between a current supplying element supplying current in accordance with the output signal from the differential amplifying circuit and a resistance element connected between the current supplying element and a power supply (ground) node.
According to a second aspect of the present invention, the semiconductor device includes a difference adjusting circuit for detecting difference in at least one of phase and frequency between an internal clock signal and an external clock signal and for generating a control signal for reducing the detected difference, a current adjusting circuit for adjusting operational current of the internal clock signal generating circuit in accordance with the output signal from the difference adjusting circuit, and a holding circuit detecting a locking state of the external clock signal and the internal clock signal for holding the output signal from the difference adjusting circuit when the locking state is detected.
According to a third aspect of the present invention, in the semiconductor device, the clock generating circuit for generating the internal clock signal includes differential amplifying circuits connected in a ring.
According to a fourth aspect of the present invention, the semiconductor device includes a comparing circuit for comparing a difference between a reference potential and an internal potential and for generating an analog signal indicative of the result of comparison; a digital converting circuit for converting an analog output signal from the comparing circuit to a digital signal; an analog charge pump circuit for adjusting gate potential of a current control transistor in accordance with the analog signal from the comparing circuit; a digital charge pump circuit for adjusting gate potential of the current control transistor in accordance with the output signal from the digital converting circuit; and a current drive transistor supplied with current from the current control transistor for supplying the current to an internal power supply node in accordance with the difference between an internal power supply potential and the reference potential.
According to a fifth aspect of the present invention, the semiconductor device includes a first current drive transistor connected between an external power supply node and an internal power supply node and receiving at its gate a reference potential; a second current drive transistor receiving at its gate the reference potential for supplying current from the external power supply node; a comparing circuit for comparing difference between the internal power supply potential and the reference potential and outputting an analog signal indicative of the difference; a digital converting circuit for converting an analog output signal from the comparing circuit to a digital signal; a third current drive transistor connected between the second current drive transistor and the internal power supply node; an analog charge pump circuit for adjusting gate potential of the third current drive transistor in accordance with the analog signal from the comparing circuit; and a digital charge pump circuit for adjusting gate potential of the third current drive transistor in accordance with an output signal from the digital converting circuit.
In the present invention, in accordance with the first aspect, even when the potential of the output signal from the differential amplifying circuit changes, the change in current of the current supplying element can be suppressed by the resistance element. Therefore, the ratio of change in current of the internal clock signal generating circuit can be made smaller as compared with the change in potential of the output signal from the difference adjusting circuit, and accordingly, sensitivity of the internal clock signal generating circuit to the output signal from the difference adjusting circuit is made smaller. Therefore, internal clock signal is locked in the external clock signal precisely with smaller jitter.
In the invention in accordance with the second aspect, the potential of the signal for adjusting current applied to the internal clock signal generating circuit while supply of the external clock signal is interrupted is maintained, and therefore the internal clock signal can be generated stably even when the external clock signal is interrupted. Further, when the external clock signal is newly supplied, adjustment of the phase/frequency of the internal clock signal starts in accordance with the maintained potential. Therefore, the internal clock signal can be synchronized with the resumed external clock signal quickly.
In the invention in accordance with the third aspect, differential amplifying circuits connected in a ring and each having complementary input/output are used for the clock generator, and therefore output signal thereof can be changed at high speed, the internal clock signal can be generated at high speed following the external clock signal, and hence the internal clock signal having its phase synchronized with high speed external clock signal can be generated.
In the invention in accordance with the fourth aspect, the gate potential of the current control transistor is adjusted combining analog and digital manners, so that the supply current of the current control transistor can be adjusted in accordance with the fluctuation of the internal power supply potential, the overshoot and the undershoot of the internal power supply potential can be suppressed, and hence the internal power supply potential can be maintained stably at a constant potential level.
In the invention in accordance with the fifth aspect, a current is supplied constantly to the internal power supply node in accordance with the difference between the reference potential and the internal power supply potential, and the gate potential of still another third current drive transistor is controlled in analog manner or digital manner in accordance with the potential at the internal power supply node. Therefore, the amount of current supplied to the internal power supply node can be adjusted in accordance with the change in the internal power supply potential, and hence the internal power supply potential can be maintained stably at a prescribed potential level.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.